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authorJonathan Zhang <jonzhang@fb.com>2020-07-08 14:26:55 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-12 19:34:28 +0000
commit0ccb3828bc6464dc51ef5075d9cc050272e0f75a (patch)
tree7537e96bf2c50dee38c0a337c45cb7a2cd41e670 /src/mainboard/roda
parentbb50c672278c7ddee146b414e219ba45e8e0f559 (diff)
vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt soc
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX. Also update IIO UDS HOB definition file accordingly. Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG. Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel is that they will converge to use FSPM_CONFIG over time. So both will co-exist for some time. Today coreboot common code expects FSP_M_CONFIG. Accomodate this situation in FspmUpd.h. The CPX-SP soc code is updated accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
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