mb/*: Remove old USB configurations from SNB/bd82x6x boards

Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.

Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 0 insertions, 67 deletions

diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
index 841b5dd091..9f37526806 100644
--- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
@@ -26,22 +26,6 @@ chip northbridge/intel/sandybridge
 	register "ec_present" = "1"
 	register "max_mem_clock_mhz" = "800"
 
-	register "usb_port_config" = "{
-		{ 1, 0, 0x0040 },
-		{ 1, 4, 0x0040 },
-		{ 1, 1, 0x0080 },
-		{ 1, 2, 0x0080 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 3, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 5, 0x0040 }, }"
-
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c
index 5de8f563d6..66e3e52038 100644
--- a/src/mainboard/roda/rv11/variants/rv11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c
@@ -8,21 +8,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	/* TODO: Confirm if need to enable peg10 in devicetree */
 	pei_data->pcie_init = 1;
 }
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* Enabled / Power / OC PIN */
-	{ 1, 0, 0 }, /* P00: 1st            USB3 (OC #0) */
-	{ 1, 0, 4 }, /* P01: 2nd            USB3 (OC #4) */
-	{ 1, 1, 1 }, /* P02: 1st Multibay   USB3 (OC #1) */
-	{ 1, 1, 2 }, /* P03: 2nd Multibay   USB3 (OC #2) */
-	{ 1, 0, 8 }, /* P04: MiniPCIe 1     USB2 (no OC) */
-	{ 1, 0, 8 }, /* P05: MiniPCIe 2     USB2 (no OC) */
-	{ 1, 0, 8 }, /* P06: MiniPCIe 3     USB2 (no OC) */
-	{ 1, 0, 8 }, /* P07: GPS            USB2 (no OC) */
-	{ 1, 0, 8 }, /* P08: MiniPCIe 4     USB2 (no OC) */
-	{ 1, 0, 3 }, /* P09: Express Card   USB2 (OC #3) */
-	{ 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */
-	{ 1, 0, 8 }, /* P11: Sensors Hub?   USB2 (no OC) */
-	{ 1, 0, 8 }, /* P12: Touch Screen   USB2 (no OC) */
-	{ 1, 0, 5 }, /* P13: reserved?      USB2 (OC #5) */
-};
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
index 783cec65ba..5c3c72b517 100644
--- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -25,21 +25,6 @@ chip northbridge/intel/sandybridge
 	register "usb3.hs_port_switch_mask" = "0xf"
 	register "usb3.preboot_support" = "1"
 	register "usb3.xhci_streams" = "1"
-	register "usb_port_config" = "{
-		{ 1, 0, 0x0080 },
-		{ 1, 0, 0x0080 },
-		{ 1, 1, 0x0080 },
-		{ 1, 1, 0x0080 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0080 },
-		{ 1, 4, 0x0080 },
-		{ 1, 5, 0x0040 },
-		{ 1, 8, 0x0040 },
-		{ 1, 8, 0x0080 },
-		{ 1, 6, 0x0080 }, }"
 
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c
index 451c4b795b..b791cbc772 100644
--- a/src/mainboard/roda/rv11/variants/rw11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c
@@ -40,21 +40,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	/* TODO: Confirm if need to enable peg10 in devicetree */
 	pei_data->pcie_init = 1;
 }
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* Enabled / Power / OC PIN */
-	{ 1, 1, 0 }, /* P00: 1st (left)     USB3 (OC #0) */
-	{ 1, 1, 0 }, /* P01: 2nd (left)     USB3 (OC #0) */
-	{ 1, 1, 1 }, /* P02: 1st Multibay   USB3 (OC #1) */
-	{ 1, 1, 1 }, /* P03: 2nd Multibay   USB3 (OC #1) */
-	{ 1, 0, 8 }, /* P04: MiniPCIe 1     USB2 (no OC) */
-	{ 1, 0, 8 }, /* P05: MiniPCIe 2     USB2 (no OC) */
-	{ 1, 0, 8 }, /* P06: USB Hub x4     USB2 (no OC) */
-	{ 1, 0, 8 }, /* P07: MiniPCIe 4     USB2 (no OC) */
-	{ 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */
-	{ 1, 1, 4 }, /* P09: 3rd (right)    USB2 (OC #4) */
-	{ 1, 0, 5 }, /* P10: 4th (right)    USB2 (OC #5) */
-	{ 1, 0, 8 }, /* P11: 3rd Multibay   USB2 (no OC) */
-	{ 1, 1, 8 }, /* P12: misc internal  USB2 (no OC) */
-	{ 1, 1, 6 }, /* P13: misc internal  USB2 (OC #6) */
-};