diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 16:44:38 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:08:33 +0000 |
| commit | 51a57eb5ea782c3287719c8c7646ea726b14c78d (patch) | |
| tree | 7ff3a6b1424750e66d4349f41eeb7fcc7b10ab77 /src/mainboard/roda/rv11/variants | |
| parent | 1acb3e118bf0bdba8f13f62304425f8c21dad2c8 (diff) | |
mb/*: Add consolidated USB port config for SNB+MRC boards
For each sandybridge boards with option to use MRC or native platform
init code, add a copy of the board's USB port config, consolidated between
both code paths, into the southbridge devicetree, using special values
allocated for this consolidation.
These get hooked up in a separate patch.
Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/roda/rv11/variants')
| -rw-r--r-- | src/mainboard/roda/rv11/variants/rv11/devicetree.cb | 17 | ||||
| -rw-r--r-- | src/mainboard/roda/rv11/variants/rw11/devicetree.cb | 17 |
2 files changed, 32 insertions, 2 deletions
diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 9da9cb88e1..841b5dd091 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -69,10 +69,25 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */ + { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */ + { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */ + { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */ + { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */ + { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */ + { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */ + { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */ + { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */ + { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */ + { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 9dae3fffa6..783cec65ba 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -73,10 +73,25 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ + { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ + { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ + { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ + { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ + { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ + { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ + { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ + { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ + { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ + { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" |