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authorSubrata Banik <subrata.banik@intel.com>2020-09-17 15:48:54 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-19 06:37:24 +0000
commite9b937352eec6e5e5b4a7e120f77f15a2732ac03 (patch)
treeb3a73a7f86096a20ce855d38f02b4077ffcb1db6 /src/mainboard/roda/rk886ex
parent8742e2a9238da49aeb4dd1afa9603fdc22697422 (diff)
apollolake boards: Enable CSE in devicetree
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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