sb/ich7: Use common/gpio.h to set up GPIOs

This is more consistent with newer Intel targets.

This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
  is ignored in native mode;
* only output pins are set high or low, since this is read-only on
  input;
* blink is only operational on output pins, non-blink is not set
  explicitly;
* invert is only operational on input pins, non-invert is not set
  explicitly.

Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

3 files changed, 118 insertions, 30 deletions

diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc
index 07db49d45f..2c68d384d1 100644
--- a/src/mainboard/roda/rk886ex/Makefile.inc
+++ b/src/mainboard/roda/rk886ex/Makefile.inc
@@ -15,3 +15,4 @@
 
 ramstage-y += m3885.c
 ramstage-y += cstates.c
+romstage-y += gpio.c
diff --git a/src/mainboard/roda/rk886ex/gpio.c b/src/mainboard/roda/rk886ex/gpio.c
new file mode 100644
index 0000000000..72868ca351
--- /dev/null
+++ b/src/mainboard/roda/rk886ex/gpio.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio6 = GPIO_MODE_GPIO, /* Enable power of SATA channel 0 */
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO, /* Wireless LAN power on */
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO, /* FAN on */
+	.gpio22 = GPIO_MODE_GPIO, /* FWH WP */
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO, /* GPS on */
+	.gpio25 = GPIO_MODE_GPIO, /* External Antenna Mux on */
+	.gpio26 = GPIO_MODE_GPIO, /* BT on */
+	.gpio27 = GPIO_MODE_GPIO, /* GSM on */
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio6 = GPIO_DIR_OUTPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio9 = GPIO_DIR_OUTPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio25 = GPIO_DIR_OUTPUT,
+	.gpio26 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio6 = GPIO_LEVEL_LOW,
+	.gpio9 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_HIGH,
+	.gpio25 = GPIO_LEVEL_LOW,
+	.gpio26 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio31 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio7 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio48 = GPIO_MODE_GPIO, /* FWH TLB# */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_OUTPUT,
+	.gpio39 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio35 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_LOW,
+	.gpio39 = GPIO_LEVEL_LOW,
+	.gpio48 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+};
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index eef3ff9532..a488488b1a 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -36,36 +36,6 @@
 #include <southbridge/intel/i82801gx/i82801gx.h>
 #include "option_table.h"
 
-void setup_ich7_gpios(void)
-{
-	printk(BIOS_DEBUG, " GPIOS...");
-	/* General Registers */
-	outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
-	outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
-	/* ------------------------------------------------------------
-	 * 0 - GPO6  - Enable power of SATA channel 0
-	 * 0 - GPO9  - Wireless LAN power on
-	 * 0 - GPO15 - FAN on
-	 * 1 - GPO22 - FWH WP
-	 * 1 - GPO24 - GPS on
-	 * 0 - GPO25 - External Antenna Mux on
-	 * 0 - GPO26 - BT on
-	 * 0 - GPO27 - GSM on
-	 */
-	outl(0x01400000, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
-	/* ------------------------------------------------------------ */
-	/* Output Control Registers */
-	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
-	/* Input Control Registers */
-	outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
-	outl(0x000100e8, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
-	outl(0x00000030, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
-	/* ------------------------------------------------------------ */
-	/* 1 - GPO48 - FWH TBL# */
-	outl(0x00010000, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL */
-	/* ------------------------------------------------------------ */
-}
-
 static void ich7_enable_lpc(void)
 {
 	int lpt_en = 0;