diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:42:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:42:32 +0000 |
| commit | c02b4fc9db3c3c1e263027382697b566127f66bb (patch) | |
| tree | 11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/mainboard/roda/rk886ex/romstage.c | |
| parent | 27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff) | |
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/roda/rk886ex/romstage.c')
| -rw-r--r-- | src/mainboard/roda/rk886ex/romstage.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 1f4b856727..4052c3277a 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -58,7 +58,7 @@ #include "southbridge/intel/i82801gx/i82801gx.h" static void setup_ich7_gpios(void) { - printk_debug(" GPIOS..."); + printk(BIOS_DEBUG, " GPIOS..."); /* General Registers */ outl(0xbfc0f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0x70a87d83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ @@ -304,7 +304,7 @@ void real_main(unsigned long bist) report_bist_failure(bist); if (MCHBAR16(SSKPD) == 0xCAFE) { - printk_debug("soft reset detected.\n"); + printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; } @@ -318,10 +318,10 @@ void real_main(unsigned long bist) /* Read PM1_CNT */ reg32 = inl(DEFAULT_PMBASE + 0x04); - printk_debug("PM1_CNT: %08x\n", reg32); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { #if CONFIG_HAVE_ACPI_RESUME - printk_debug("Resume from S3 detected.\n"); + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. @@ -329,7 +329,7 @@ void real_main(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); #else - printk_debug("Resume from S3 detected, but disabled.\n"); + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); #endif } @@ -365,7 +365,7 @@ void real_main(unsigned long bist) /* This will not work if TSEG is in place! */ u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - printk_debug("TOM: 0x%08x\n", tom); + printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); ram_check(0x00000000, 0x000a0000); ram_check(0x00100000, tom); } |