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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-21 17:29:59 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-21 17:29:59 +0000
commit57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch)
tree3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/rca
parent5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff)
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/rca')
-rw-r--r--src/mainboard/rca/rm4100/romstage.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index eec73a1942..c974ebeedd 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -36,12 +36,11 @@
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
@@ -128,4 +127,3 @@ void main(unsigned long bist)
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
}
-