Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830

Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000

Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

9 files changed, 0 insertions, 460 deletions

diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
deleted file mode 100644
index 81cfc7b999..0000000000
--- a/src/mainboard/rca/rm4100/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if BOARD_RCA_RM4100
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_MFCBGA479
-	select NORTHBRIDGE_INTEL_I82830
-	select SOUTHBRIDGE_INTEL_I82801DX
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_PIRQ_TABLE
-	select BOARD_ROMSIZE_KB_1024
-
-config MAINBOARD_DIR
-	string
-	default rca/rm4100
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "RM4100"
-
-config IRQ_SLOT_COUNT
-	int
-	default 7
-
-endif # BOARD_RCA_RM4100
diff --git a/src/mainboard/rca/rm4100/Kconfig.name b/src/mainboard/rca/rm4100/Kconfig.name
deleted file mode 100644
index fd737abbd1..0000000000
--- a/src/mainboard/rca/rm4100/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_RCA_RM4100
-	bool "RM4100"
diff --git a/src/mainboard/rca/rm4100/board_info.txt b/src/mainboard/rca/rm4100/board_info.txt
deleted file mode 100644
index 0c06a7d7eb..0000000000
--- a/src/mainboard/rca/rm4100/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.settoplinux.org/index.php?title=RCA_RM4100
-Flashrom support: y
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
deleted file mode 100644
index 7c31423c6d..0000000000
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ /dev/null
@@ -1,67 +0,0 @@
-chip northbridge/intel/i82830		# Northbridge
-  device cpu_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_mFCBGA479	# Mobile Celeron Micro-FCBGA Socket 479
-      device lapic 0 on end		# APIC
-    end
-  end
-  device domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 2.0 on end		# VGA (Intel 82830 CGC)
-    chip southbridge/intel/i82801dx	# Southbridge
-      register "pirqa_routing" = "0x05"
-      register "pirqb_routing" = "0x06"
-      register "pirqc_routing" = "0x07"
-      register "pirqd_routing" = "0x09"
-      register "pirqe_routing" = "0x0a"
-      register "pirqf_routing" = "0x80"
-      register "pirqg_routing" = "0x80"
-      register "pirqh_routing" = "0x0b"
-
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1d.0 on end		# USB UHCI Controller #1
-      device pci 1d.1 on end		# USB UHCI Controller #2
-      device pci 1d.2 on end		# USB UHCI Controller #3
-      device pci 1d.7 on end		# USB2 EHCI Controller
-      device pci 1e.0 on end		# PCI bridge
-      device pci 1f.0 on		# ISA/LPC bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 2e.4 on		# Com1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 on		# Com2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.7 on		# PS/2 keyboard/mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# Keyboard interrupt
-            irq 0x72 = 12		# Mouse interrupt
-          end
-          device pnp 2e.9 off end	# Game port
-          device pnp 2e.a on		# PME
-            io 0x60 = 0x800
-          end
-          device pnp 2e.b off end	# MPU-401
-        end
-      end
-      device pci 1f.1 on end		# IDE
-      device pci 1f.3 on end		# SMBus
-      device pci 1f.5 on end		# AC'97 audio
-      device pci 1f.6 on end		# AC'97 modem
-    end
-  end
-end
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c
deleted file mode 100644
index 168bb09def..0000000000
--- a/src/mainboard/rca/rm4100/gpio.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-
-#define PME_DEV			PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-#define ICH_IO_BASE_ADDR	0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	pci_devfn_t dev;
-	uint16_t port;
-	uint32_t set_gpio;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL, 0x10);
-
-	/* Set GPIO23 to high, this enables the LAN controller. */
-	udelay(10);
-	set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
-	set_gpio |= 1 << 23;
-	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	/* Enter the configuration state. */
-	outb(0x55, port);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-
-	/* GP21 - LED_RED */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
-	/* GP30 - FAN2_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
-	/* GP31 - FAN1_TACH */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
-	/* GP32 - FAN2_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
-	/* GP33 - FAN1_CTRL */
-	outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
-	/* GP34 - AUD_MUTE_OUT_R */
-	outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
-	/* GP36 - KBRST */
-	outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
-	/* GP37 - A20GATE */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
-	/* GP42 - GPIO_PME_OUT */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
-	/* GP50 - SER2_RI */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
-	/* GP51 - SER2_DCD */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
-	/* GP52 - SER2_RX */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
-	/* GP53 - SER2_TX */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
-	/* GP55 - SER2_RTS */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
-	/* GP56 - SER2_CTS */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
-	/* GP57 - SER2_DTR */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
-	/* GP60 - LED_GREEN */
-	outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
-	/* GP61 - LED_YELLOW */
-	outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
-	/* GP3 */
-	outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
-	/* GP4 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
-	/* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
-	/* FAN2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
-	/* Fan Control */
-	outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
-	/* Fan1 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
-	/* Fan2 Tachometer */
-	outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
-	/* LED1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
-	/* LED2 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
-	/* Keyboard Scan Code */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
-	/* Exit the configuration state. */
-	outb(0xaa, port);
-}
diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c
deleted file mode 100644
index e99adfcbc5..0000000000
--- a/src/mainboard/rca/rm4100/irq_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x24c0,		 /* Device */
-	0,		 /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x07,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
-		{0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
-		{0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
-		{0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
-		{0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
-		{0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
-		{0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
deleted file mode 100644
index 43c518f428..0000000000
--- a/src/mainboard/rca/rm4100/romstage.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <lib.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/intel/i82830/raminit.h>
-#include "northbridge/intel/i82830/memory_initialized.c"
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include "southbridge/intel/i82801dx/reset.c"
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include "spd_table.h"
-#include "gpio.c"
-#include "southbridge/intel/i82801dx/tco_timer.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-/**
- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
- * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
- * (0x51/DIMM1).
- */
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-	int i;
-
-	if (device == DIMM0) {
-		return smbus_read_byte(device, address);
-	} else if (device == DIMM1) {
-		for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
-			if (spd_table[i].address == address)
-				return spd_table[i].data;
-		}
-		return 0xFF; /* Return 0xFF when address is not found. */
-	} else {
-		return 0xFF; /* Return 0xFF on any failures. */
-	}
-}
-
-#include "northbridge/intel/i82830/raminit.c"
-
-/**
- * Setup mainboard specific registers pre raminit.
- */
-static void mb_early_setup(void)
-{
-	/* - Hub Interface to PCI Bridge Registers - */
-	/* 12-Clock Retry Enable */
-	pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
-	/* Master Latency Timer Count */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
-	/* I/O Address Base */
-	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
-
-	/* - LPC Interface Bridge Registers - */
-	/* Delayed Transaction Enable */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
-	/* Disable the TCO Timer system reboot feature */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
-	/* CPU Frequency Strap */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
-	/* ACPI base address and enable Resource Indicator */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
-	/* Enable the SMBUS */
-	enable_smbus();
-	/* ACPI base address and disable Resource Indicator */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
-	/*  ACPI Enable */
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	if (bist == 0) {
-		if (memory_initialized())
-			hard_reset();
-	}
-
-	/* Set southbridge and superio gpios */
-	mb_gpio_init();
-
-	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure. */
-	report_bist_failure(bist);
-
-	/* disable TCO timers */
-	i82801dx_halt_tco_timer();
-
-	/* Setup mainboard specific registers */
-	mb_early_setup();
-
-	/* Initialize memory */
-	sdram_initialize();
-}
diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c
deleted file mode 100644
index a8a7aca9f1..0000000000
--- a/src/mainboard/rca/rm4100/smihandler.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
-	printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
-	return 1;
-}
diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h
deleted file mode 100644
index 14bc85b724..0000000000
--- a/src/mainboard/rca/rm4100/spd_table.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-struct spd_entry {
-	unsigned int address;
-	unsigned int data;
-};
-
-/*
- * The onboard 128MB PC133 memory does not have an SPD EEPROM so the values
- * have to be set manually, the onboard memory is located in socket1 (0x51).
- */
-const struct spd_entry spd_table [] = {
-	{SPD_MEMORY_TYPE,                     0x04}, /* (Fundamental) memory type */
-	{SPD_NUM_COLUMNS,                     0x09}, /* Number of column address bits */
-	{SPD_NUM_DIMM_BANKS,                  0x01}, /* Number of module rows (banks) */
-	{SPD_MODULE_DATA_WIDTH_LSB,           0x40}, /* Module data width (LSB) */
-	{SPD_MIN_CYCLE_TIME_AT_CAS_MAX,       0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
-	{SPD_ACCESS_TIME_FROM_CLOCK,          0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
-	{SPD_DENSITY_OF_EACH_ROW_ON_MODULE,   0x20}, /* Density of each row on module */
-};