diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-10-23 17:37:21 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-10-28 18:42:46 +0000 |
| commit | 9a1b47e8a005e87ed6be0c8d62c62e5e7007b3e3 (patch) | |
| tree | 6ecd08976f478d5e7f3984637bf59e984ac00998 /src/mainboard/razer | |
| parent | d5008a2e8289ff98a42f27a0f263e0fd0b47bfc2 (diff) | |
mb/{sm/x11,razor,libretrend}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they will be moved
into the devicetree to their related root ports at some later point.
While on it, remove superfluous comments related to modified lines.
Change-Id: I27bac17098beb8b6cb3942e68a37da0095f0d0bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/razer')
| -rw-r--r-- | src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 40 |
1 files changed, 21 insertions, 19 deletions
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 9e6d4fbd81..f88c99d0c7 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,9 +23,11 @@ chip soc/intel/skylake # FSP Configuration register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "0" - register "SataPortsEnable[1]" = "0" - register "SataPortsEnable[2]" = "0" + register "SataPortsEnable" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + }" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" @@ -124,23 +126,23 @@ chip soc/intel/skylake register "PcieRpHotPlug[4]" = "1" - # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (left) - - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # TODO Unknown. Maybe USBC? - - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC2)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC2)" # Keyboard - register "usb2_ports[8]" = "USB2_PORT_FLEX(OC2)" # Touchscreen - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left) - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */ + [2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [6] = USB2_PORT_FLEX(OC2), /* Camera */ + [7] = USB2_PORT_FLEX(OC2), /* Keyboard */ + [8] = USB2_PORT_FLEX(OC2), /* Touchscreen */ + }" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC? + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */ + [1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */ + [5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */ + }" # PL1 override 25W # PL2 override 44W |