diff options
| author | John Zhao <john.zhao@intel.com> | 2020-06-30 15:44:44 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-07 17:26:08 +0000 |
| commit | 7b46aae06205e22b4e0afe51c78770e0983e3dde (patch) | |
| tree | baaa320a47be198cc0f002afa90ab71917ab1063 /src/mainboard/razer | |
| parent | 4db893b6fc8d299d334803d46898d00f961a0c9a (diff) | |
mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3
Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.
TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP
board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42953
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/razer')
0 files changed, 0 insertions, 0 deletions