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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-04-02 15:31:21 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-05 19:10:05 +0000 |
| commit | a5c27096a41a715efda103b03bf3ce2a61ff1670 (patch) | |
| tree | 93dd364d4665b47c6fa7bf59749efb87c994c151 /src/mainboard/razer/blade_stealth_kbl | |
| parent | e67ab180fb856b25f3fbb238438606446a7e3ddb (diff) | |
soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.
This change updates memory configuration on Tiger Lake Platform to
replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds().
For reference https://review.coreboot.org/c/coreboot/+/39797 added
"DisableDimmCh#" UPD.
BUG=b:152000235
BRANCH=none
TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40061
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/razer/blade_stealth_kbl')
0 files changed, 0 insertions, 0 deletions