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authorNico Huber <nico.h@gmx.de>2024-01-12 16:22:19 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-02-19 13:18:17 +0000
commit3d80d14cd4ed82e74057cea884dcb9bb7588c076 (patch)
tree2b871fd211af0a239a0926f28c787e3cd406cc90 /src/mainboard/purism
parent9bf38c7d672dbfe0771a15574a7e0c59f38c139c (diff)
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/purism')
-rw-r--r--src/mainboard/purism/librem_jsl/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_jsl/devicetree.cb b/src/mainboard/purism/librem_jsl/devicetree.cb
index e3b3be2022..c992c4f2bc 100644
--- a/src/mainboard/purism/librem_jsl/devicetree.cb
+++ b/src/mainboard/purism/librem_jsl/devicetree.cb
@@ -159,7 +159,6 @@ chip soc/intel/jasperlake
device pci 1c.0 off end # PCI Express Root Port 1
device pci 1c.1 off end # PCI Express Root Port 2
device pci 1c.2 on # PCI Express Root Port 3 - M.2 M-key, PCIe only
- register "PcieRpEnable[2]" = "true"
register "PcieClkSrcUsage[0]" = "2"
register "PcieClkSrcClkReq[0]" = "0"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X"