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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-06-28 10:18:29 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-03 12:48:33 +0000 |
| commit | 15e1d97463f8ae21010f6f6bf38659b6cae718b2 (patch) | |
| tree | 0d6d20050e29cf25cf589d109143943dc3e2c01c /src/mainboard/purism | |
| parent | b34576b03bc9034843969505d6193ea22837e36c (diff) | |
mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.
Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/purism')
0 files changed, 0 insertions, 0 deletions