diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/purism | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/purism')
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb | 32 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb | 37 |
2 files changed, 40 insertions, 29 deletions
diff --git a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb index 18ce220753..08cf745487 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb @@ -1,17 +1,23 @@ chip soc/intel/skylake - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD + device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port + [1] = USB2_PORT_MID(OC0), // Type-A Port (right) + [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [3] = USB2_PORT_FLEX(OC_SKIP), // Camera + [5] = USB2_PORT_FLEX(OC2), // Type-A Port (left) + [6] = USB2_PORT_MID(OC_SKIP), // SD + }" - # OC1 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - - device domain 0 on end + # OC1 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + [1] = USB3_PORT_DEFAULT(OC0), // Type-A Port (right) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + }" + end + end end diff --git a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb index 343944ee42..fa76a780f5 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15/overridetree.cb @@ -5,23 +5,28 @@ chip soc/intel/skylake # SRCCLKREQ2# for NVMe per schematic register "PcieRpClkReqNumber[8]" = "2" - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) - register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera - register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD - - # OC0 should be for Type-C but it seems to not have been wired, according to - # the available schematics, even though it is labeled as USB_OC_TYPEC. - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port - device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port + [1] = USB2_PORT_MID(OC1), // Type-A Port (right) + [2] = USB2_PORT_MID(OC1), // Type-A Port (right) + [3] = USB2_PORT_FLEX(OC2), // Type-A Port (left) + [4] = USB2_PORT_FLEX(OC2), // Type-A Port (left) + [5] = USB2_PORT_MID(OC_SKIP), // Bluetooth + [6] = USB2_PORT_FLEX(OC_SKIP), // Camera + [7] = USB2_PORT_FLEX(OC_SKIP), // SD + }" + + # OC0 should be for Type-C but it seems to not have been wired, according to + # the available schematics, even though it is labeled as USB_OC_TYPEC. + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + [1] = USB3_PORT_DEFAULT(OC1), // Type-A Port (right) + [2] = USB3_PORT_DEFAULT(OC1), // Type-A Port (right) + [3] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port + }" + end device ref pcie_rp5 on end end end |