mb/purism/librem_whl: Add new board Librem Mini (WHL-U)

Add new librem_whl baseboard and Librem Mini variant.

Tested with SeaBIOS, Tianocore, and Heads payloads.

All functions working normally except SATA, which is limited
via a FSP UPD to 3Gbps until the correct HSIO PHY settings
can be determined.

https://puri.sm/products/librem-mini/

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c
new file mode 100644
index 0000000000..07ede66505
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/ramstage.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	size_t num_gpios;
+	const struct pad_config *gpio_table = variant_gpio_table(&num_gpios);
+	cnl_configure_pads(gpio_table, num_gpios);
+
+	/* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */
+	params->SataSpeedLimit = 2;
+}