mb/purism/librem_whl: Add new board Librem Mini (WHL-U)

Add new librem_whl baseboard and Librem Mini variant.

Tested with SeaBIOS, Tianocore, and Heads payloads.

All functions working normally except SATA, which is limited
via a FSP UPD to 3Gbps until the correct HSIO PHY settings
can be determined.

https://puri.sm/products/librem-mini/

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 26 insertions, 0 deletions

diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl
new file mode 100644
index 0000000000..296be17b35
--- /dev/null
+++ b/src/mainboard/purism/librem_whl/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	#include <soc/intel/cannonlake/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/cannonlake/acpi/southbridge.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	#include "acpi/mainboard.asl"
+}