diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-07-19 11:59:50 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2024-08-28 00:35:27 +0000 |
| commit | 8c4d7e7e9112d079687a1679799c659b576e96cb (patch) | |
| tree | bf591eb03470ed8b79ea9a524827ecdf64344c9b /src/mainboard/purism/librem_cnl | |
| parent | 9c8debf6b53c451559f4372ab9c7682b860f8fd6 (diff) | |
tree: Use boolean for "eist_enable"
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Diffstat (limited to 'src/mainboard/purism/librem_cnl')
| -rw-r--r-- | src/mainboard/purism/librem_cnl/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb index cc1433d7d4..dfacdea686 100644 --- a/src/mainboard/purism/librem_cnl/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + register "eist_enable" = "true" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) register "SaGv" = "SaGv_Enabled" |