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authorJonathon Hall <jonathon.hall@puri.sm>2022-11-16 09:51:25 -0500
committerFelix Held <felix-coreboot@felixheld.de>2022-12-02 14:49:13 +0000
commitdef33cc5bb4d37d1b7131c45ae064a648b88bdab (patch)
treeedca9c4b84185a73e69bd799e0a89a5255474934 /src/mainboard/purism/librem_cnl
parent13e151f31ce25dce4116214d7e3329506e029887 (diff)
mb/purism/librem_14: Enable both lanes of left side USB 3.0 port
Fixes using USB-C devices in either orientation on left-side USB-C port. Test: Plug USB-C device in both orientations on left-side USB-C port, check speed with lsusb -t. Change-Id: I9fbc53bb51a5225e92b0b6bb9ced87a0ab90c9ce Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69702 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/purism/librem_cnl')
-rw-r--r--src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
index b979740f8d..ef35ac099d 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
@@ -127,6 +127,7 @@ chip soc/intel/cannonlake
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A right
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A left
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-C right
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-C left
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
end