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authorYouness Alaoui <youness.alaoui@puri.sm>2017-05-25 15:30:35 -0500
committerMartin Roth <martinroth@google.com>2017-06-09 17:02:42 +0200
commit9d8cd507a60c625c78dec68ab7cfd2d27799f513 (patch)
tree5a63b7d84f7eadc5b132b138381038ecc0890999 /src/mainboard/purism/librem13v2
parent6b8570d86419a5b4a358504773e60f6e4019dc48 (diff)
purism/librem13v2: Enable SATA, disable eMMC support
Change-Id: Ib63e5e8a1bcbc25c288dec7d1ef6c06239ada34b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/purism/librem13v2')
-rw-r--r--src/mainboard/purism/librem13v2/devicetree.cb9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index 0b49433cb9..dc0655af50 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -28,10 +28,11 @@ chip soc/intel/skylake
# FSP Configuration
register "ProbelessTrace" = "0"
register "EnableLan" = "0"
- register "EnableSata" = "0"
+ register "EnableSata" = "1"
register "SataSalpSupport" = "0"
register "SataMode" = "0"
- register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[2]" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
@@ -40,8 +41,8 @@ chip soc/intel/skylake
register "SsicPortEnable" = "0"
register "SmbusEnable" = "1"
register "Cio2Enable" = "0"
- register "ScsEmmcEnabled" = "1"
- register "ScsEmmcHs400Enabled" = "1"
+ register "ScsEmmcEnabled" = "0"
+ register "ScsEmmcHs400Enabled" = "0"
register "ScsSdCardEnabled" = "0"
register "IshEnable" = "0"
register "PttSwitch" = "0"