diff options
author | Matt DeVillier <matt.devillier@gmail.com> | 2017-06-22 15:54:07 -0400 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-10-23 16:56:37 +0000 |
commit | fb1cd09596cfbbaa3b4ec7ec45b6ec8d8fa52411 (patch) | |
tree | e1bac936617080050542518c8dc312917100b893 /src/mainboard/purism/librem13v2/pei_data.c | |
parent | 9b6384c1a585f1d34b99025281aa9dfd4ed19735 (diff) |
purism/librem13v2: migrate from FSP 1.1 to 2.0
Migrate the Librem13v2 from using FSP 1.1 to
the public/GitHub FSP 2.0 Skylake/Kabylake release:
- select FSP 2.0 in Kconfig
- adjust romstage/ramstage functions as required
- refactor pei_data functions
- remove VR_RING domain from devicetree (unsupported in FSP 2.0)
- add SataSpeedLimit parameter to work around power-related issue
when operating at SATA 6.0Gbps speed
TEST: build/boot Librem13v2, observe successful boot, lack of
SATA-related errors in dmesg.
Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/purism/librem13v2/pei_data.c')
-rw-r--r-- | src/mainboard/purism/librem13v2/pei_data.c | 32 |
1 files changed, 25 insertions, 7 deletions
diff --git a/src/mainboard/purism/librem13v2/pei_data.c b/src/mainboard/purism/librem13v2/pei_data.c index 730b7307be..0be917d3c7 100644 --- a/src/mainboard/purism/librem13v2/pei_data.c +++ b/src/mainboard/purism/librem13v2/pei_data.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,8 +19,9 @@ #include <string.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> +#include "pei_data.h" -void mainboard_fill_pei_data(struct pei_data *pei_data) +void mainboard_fill_dq_map_data(void *dq_map_ptr) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -27,21 +29,37 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ /* Rcomp resistor */ const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); } |