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authorMichał Żygowski <michal.zygowski@3mdeb.com>2019-06-27 12:19:18 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-03-10 10:03:17 +0000
commit48be6b276a0d7d0376684eaa5c1d92b763f61cc6 (patch)
tree96bd243fc9d7e1425bb55bab98e269112ec911bb /src/mainboard/protectli/vault_kbl/ramstage.c
parentdcd3d072d4760d9040b61d34c5ee6663a963fb54 (diff)
mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/protectli/vault_kbl/ramstage.c')
-rw-r--r--src/mainboard/protectli/vault_kbl/ramstage.c21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c
new file mode 100644
index 0000000000..e9273ba907
--- /dev/null
+++ b/src/mainboard/protectli/vault_kbl/ramstage.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* This file is part of the coreboot project. */
+
+#include <bootstate.h>
+#include <soc/ramstage.h>
+
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /*
+ * Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization.
+ */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+ params->TurboMode = 1;
+ params->PchThermalDeviceEnable = 0;
+ params->PchPort61hEnable = 1;
+ params->CdClock = 3;
+}