diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-06-27 07:17:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-30 05:58:08 +0000 |
| commit | bda27cd336a784d6ac55b2eb8af2635b26545fc4 (patch) | |
| tree | 0c11a4b0c20cb24d3fbc49f7bc66e07e5e855b6f /src/mainboard/prodrive/hermes | |
| parent | e8d230d65d9cba20da77d0c5d200edf40286e09d (diff) | |
src: Remove whitespaces before tabs
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/prodrive/hermes')
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index c55ac92dc3..532254bdf0 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -34,7 +34,7 @@ chip soc/intel/cannonlake device pci 00.0 on end # Aspeed 2500 VGA end end # PCIe - device pci 1f.0 on # LPC Interface + device pci 1f.0 on # LPC Interface chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 93bae8031f..a56096ec04 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -25,7 +25,7 @@ chip soc/intel/cannonlake # Enumeration starts at 0 for PCIE1 # Ports are not hotplugable register "PcieRpEnable[0]" = "1" # Slot3 x4 - # Set MaxPayload to 256 bytes + # Set MaxPayload to 256 bytes register "PcieRpMaxPayload[0]" = "RpMaxPayload_256" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" |