mb/prodrive/hermes: Prevent SGPIO cross-powering 5V rail

The PCH's SGPIO pads are connected to a buffer chip that is powered from
the always-on +3V3_AUX rail. For some cursed reason, when the SGPIO pads
stay configured as SGPIO when a Poseidon system shuts down, voltage from
the +3V3_AUX-powered buffer chip will leak into the +5V rail through the
SATA backplane. Just pulling the SGPIO pads low before the system powers
off stops the +5V rail from being cross-powered.

This issue has only been observed in S5, but it's very likely other
sleep states are affected as well. Thus, always pull the SGPIO pins
low before entering ACPI S3 or deeper because the power supply will
turn off in these states as well.

TEST=Obtain a Poseidon system, verify that the +5V rail is cross-powered
     after going to S5. We measured 0.17V on our system, but voltages as
     high as 0.6V were measured on other systems. Verify that unplugging
     the SGPIO cable going to the SATA backplane results in the +5V rail
     voltage dropping to 0V, which indicates that the voltage leakage is
     exclusively coming from the SGPIO and SATA backplane. Finally, make
     sure that the +5V rail voltage drops to 0V after going into ACPI S5
     with this patch applied and the SGPIO cable connected.

Change-Id: Ic872903d5fcdd1c17e02b4c06d5ba29889fbc27d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/src/mainboard/prodrive/hermes/smihandler.c b/src/mainboard/prodrive/hermes/smihandler.c
new file mode 100644
index 0000000000..50b8e8b0a0
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/smihandler.c
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <cpu/x86/smm.h>
+#include <intelblocks/gpio.h>
+#include <intelblocks/smihandler.h>
+#include <soc/gpio.h>
+
+static const struct pad_config sgpio_table[] = {
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_CFG_GPO(GPP_F11, 0, DEEP),
+	PAD_CFG_GPO(GPP_F12, 0, DEEP),
+	PAD_CFG_GPO(GPP_F13, 0, DEEP),
+};
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	/*
+	 * Pull SGPIO pins low to prevent cross-powering the +5V rail
+	 * through the SATA backplane when the power supply is off.
+	 */
+	if (slp_typ >= ACPI_S3)
+		gpio_configure_pads(sgpio_table, ARRAY_SIZE(sgpio_table));
+}