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authorChristian Walter <christian.walter@9elements.com>2020-01-09 15:42:42 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2020-06-06 07:44:53 +0000
commitb646e28769f27ee2812925f63fe2f73c67e23c9e (patch)
tree271b049fe1671304da6425c2f90fff0bffabec90 /src/mainboard/prodrive/hermes/ramstage.c
parentb7cf7d36d7cf97b0cce437b9f1577ca39eeb312d (diff)
mb/prodrive/hermes: Add new mainboard port
This patch adds support for the Prodrive Hermes mainboard. Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41. Untested: * CNVi * Intel Graphics Tested: * CPU Intel Xeon E2288G * CPU Intel Core i3-9100F * CPU Intel Core i7 9700KF * CPU Intel Core i7 9700E * CPU Intel Core i7 9700F * CPU Intel Core i5 9600K * CPU Intel Pentium Gold G5400 * PCIe Link Width x8 on Slot6 by changing PCIe mux * All four DDR4 slots in different configurations * USB2.0 HDR1 * USB2.0 HDR2 * USB3.0 HDR * Slot1 * Slot2 * Slot3 * Slot4 * Slot6 * M2.M NVMEe * Ethernet PHYs 0-4 * Aspeed BMC PCIe * Aspeed BMC USB * Aspeed Graphics init * USB3 backplane all working * I801 SMBUS Not Working: * Intel HDA Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862 Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/prodrive/hermes/ramstage.c')
-rw-r--r--src/mainboard/prodrive/hermes/ramstage.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c
new file mode 100644
index 0000000000..18fc915018
--- /dev/null
+++ b/src/mainboard/prodrive/hermes/ramstage.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+#include "variants/baseboard/include/eeprom.h"
+
+static fsp_params parmas_list[] = {
+ // FIXME: Fill with additional options
+};
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ size_t num = 0;
+ const struct pad_config *gpio_table = get_gpio_table(&num);
+
+ /* Configure pads prior to SiliconInit() in case there's any
+ dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, num);
+
+ params->SataLedEnable = 1;
+
+ // Overwrite params
+ if (!check_signature(I2C_ADDR_EEPROM))
+ return;
+
+ for (u8 i = 0; i <= ARRAY_SIZE(parmas_list); i++) {
+ if (ARRAY_SIZE(parmas_list) == 0)
+ break;
+ read_write_config(I2C_ADDR_EEPROM, params, EEPROM_OFFSET_FSP_CONFIG +
+ parmas_list[i].offset,
+ EEPROM_OFFSET_FSP_CONFIG + parmas_list[i].offset,
+ parmas_list[i].size);
+ }
+}