diff options
author | Christian Walter <christian.walter@9elements.com> | 2020-01-09 15:42:42 +0100 |
---|---|---|
committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-06-06 07:44:53 +0000 |
commit | b646e28769f27ee2812925f63fe2f73c67e23c9e (patch) | |
tree | 271b049fe1671304da6425c2f90fff0bffabec90 /src/mainboard/prodrive/hermes/mainboard.c | |
parent | b7cf7d36d7cf97b0cce437b9f1577ca39eeb312d (diff) |
mb/prodrive/hermes: Add new mainboard port
This patch adds support for the Prodrive Hermes mainboard.
Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41.
Untested:
* CNVi
* Intel Graphics
Tested:
* CPU Intel Xeon E2288G
* CPU Intel Core i3-9100F
* CPU Intel Core i7 9700KF
* CPU Intel Core i7 9700E
* CPU Intel Core i7 9700F
* CPU Intel Core i5 9600K
* CPU Intel Pentium Gold G5400
* PCIe Link Width x8 on Slot6 by changing PCIe mux
* All four DDR4 slots in different configurations
* USB2.0 HDR1
* USB2.0 HDR2
* USB3.0 HDR
* Slot1
* Slot2
* Slot3
* Slot4
* Slot6
* M2.M NVMEe
* Ethernet PHYs 0-4
* Aspeed BMC PCIe
* Aspeed BMC USB
* Aspeed Graphics init
* USB3 backplane all working
* I801 SMBUS
Not Working:
* Intel HDA
Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/prodrive/hermes/mainboard.c')
-rw-r--r-- | src/mainboard/prodrive/hermes/mainboard.c | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c new file mode 100644 index 0000000000..b24dd566f9 --- /dev/null +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include "gpio.h" + +/* FIXME: Example code below */ + +static void mb_configure_dp1_pwr(bool enable) +{ + gpio_output(GPP_K3, enable); +} + +static void mb_configure_dp2_pwr(bool enable) +{ + gpio_output(GPP_K4, enable); +} + +static void mb_configure_dp3_pwr(bool enable) +{ + gpio_output(GPP_K5, enable); +} + +static void mb_pcie_reset_pch_slots(bool enable) +{ + gpio_output(GPP_K0, enable); +} + +static void mb_pcie_reset_cpu_slots(bool enable) +{ + gpio_output(GPP_K1, enable); +} + +static void mb_pcie_reset_cnvi_slot(bool enable) +{ + gpio_output(GPP_K2, enable); +} + +static void mb_hda_amp_enable(bool enable) +{ + gpio_output(GPP_C19, enable); +} + +static void mb_usb31_rp1_pwr_enable(bool enable) +{ + gpio_output(GPP_G0, enable); +} + +static void mb_usb31_rp2_pwr_enable(bool enable) +{ + gpio_output(GPP_G1, enable); +} + +static void mb_usb31_fp_pwr_enable(bool enable) +{ + gpio_output(GPP_G2, enable); +} + +static void mb_usb2_fp1_pwr_enable(bool enable) +{ + gpio_output(GPP_G3, enable); +} + +static void mb_usb2_fp2_pwr_enable(bool enable) +{ + gpio_output(GPP_G4, enable); +} + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: Do runtime configuration once the board is production ready */ + mb_configure_dp1_pwr(1); + mb_configure_dp2_pwr(1); + mb_configure_dp3_pwr(1); + if (0) { + mb_pcie_reset_pch_slots(1); + mb_pcie_reset_cpu_slots(0); + mb_pcie_reset_cnvi_slot(0); + } + mb_hda_amp_enable(1); + mb_usb31_rp1_pwr_enable(1); + mb_usb31_rp2_pwr_enable(1); + mb_usb31_fp_pwr_enable(1); + mb_usb2_fp1_pwr_enable(1); + mb_usb2_fp2_pwr_enable(1); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; |