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author | Edward O'Callaghan <quasisec@google.com> | 2020-08-14 12:27:42 +1000 |
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committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-08-22 01:30:42 +0000 |
commit | bd409ad69f6f33681bc5cde65cc72eedbd8d2abc (patch) | |
tree | bb95e754205c61ff37f9f3d1fac7605110eef2d2 /src/mainboard/prodrive/hermes/eeprom.c | |
parent | d329417062fdf30a895057d127217eba042d02e9 (diff) |
mb/google/puff: Select cse_board_reset() strong symbol
Since Puff uses CSE Lite SKU that supports in-field CSME
updates an additional reset is triggered when jmp from RO
to RW during boot. However this reset is not detected by
the cr50 running older firmware because the strapping
configuration for EFS2 uses PLT_RST_L to assert to cr50
that a AP reset occured. The older cr50 firmware
version of 0.0.22 only monitors AP resets via SYS_RESET_L
and hence never detects the reset.
To mitigate the issue above a modified reset sequence is
required to be performed to signal the reset occured and
hence a board-specific cse_board_reset() strong symbol is
provided to modify the flow accordingly.
V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common
implementation instead of a local variant in mainboard.c
BUG=b:162290856
BRANCH=puff
TEST=none
Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/prodrive/hermes/eeprom.c')
0 files changed, 0 insertions, 0 deletions