diff options
| author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | 2022-03-07 18:39:17 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2022-03-15 18:10:41 +0000 |
| commit | 215a97ee1c4cd87b266d63e32bf0b379e18fe849 (patch) | |
| tree | c6ef1cae5509d9328198e9b468b55ad3e5d53791 /src/mainboard/prodrive/atlas | |
| parent | 6207a3967e0efeb0b52e24bc82b16e53085b6b9b (diff) | |
soc/intel/adl/chip.h: Convert all camel case variables to snake case
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/prodrive/atlas')
| -rw-r--r-- | src/mainboard/prodrive/atlas/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 7b094e4fc0..8476c482eb 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -23,19 +23,19 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" - register "SataSalpSupport" = "1" + register "sata_salp_support" = "1" - register "SataPortsEnable" = "{ + register "sata_ports_enable" = "{ [0] = 1, [1] = 1, }" - register "SataPortsDevSlp" = "{ + register "sata_ports_dev_slp" = "{ [0] = 1, [1] = 1, }" - register "SerialIoUartMode" = "{ + register "serial_io_uart_mode" = "{ [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoDisabled, |