diff options
author | Maximilian Brune <maximilian.brune@9elements.com> | 2023-02-23 19:07:41 +0100 |
---|---|---|
committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-21 11:36:32 +0000 |
commit | 4f13239318a92451dddcc821d9fb977c1d0b6994 (patch) | |
tree | 6ff4204b2cbc69f617eaf272a17112cdd77de574 /src/mainboard/prodrive/atlas/devicetree.cb | |
parent | b8fc81d8580e6fe8b0a274930d42c53f81d94011 (diff) |
mb/prodrive/atlas: Configure PCIe CLKREQ
Intel Client PCIe* controller expects each device should drive the
SRCCLKREQ#. If the GPIO is set to native mode for a device, which does
not support SRCCLKREQ#, then during RTD3 exit link would not be
established. Because controller samples the SRCCLKREQ# before
detecting the device and break L1 as the system might enter L1SS as
controller detects SRCCLKREQ# as de-asserted.
As a workaround the Pins must not be configured in Native Mode (CLKREQ
native function). Therefore here they are not configured at all.
source: 689882 (intel document ID)
So apparently hardware doesn't sample SRCCLKREQ Pin if it's not
configured as such.
That workaround suggestion however also brought a patch to FSP, which
in turn causes the same bug (even if SRCLKREQ are not configured).
Usually in order to make use of root port power saving features (e.g.
clock gating), the Root port must either be disabled or a CLKREQ Pin
must be configured. The patch however removed that check before
enabling power management for the rootport.
Workaround (until FSP is fixed):
pretend to FSP that the rootports have a CLKREQ Pin attached, by
supplying them in the FSP UPDs. That will cause FSP to configure the
CLKREQ Pin and enable power management for said rootport, but it will
not crash on L1 entry/exit. That has been done on the Atlas board
(as workaround) for a short period of time (before applying FSP Fix)
like this:
// RP 5 (the rootport you want to fix)
- memupd->FspmConfig.PcieClkSrcUsage[2] = 4;
// e.g. choose a clkreq pin that is not routed out
- memupd->FspmConfig.PcieClkSrcClkReq[2] = 0;
Furthermore disable CpuPcieRpClockReqMsgEnable FSP-M options to prevent
the same issue, but for CPU root ports. If not done the following will
happen in coreboot:
[DEBUG] PCI: 00:06.2 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:06.2
[DEBUG] PCI: pci_scan_bus for bus 02
[DEBUG] PCI: 02:00.0 [1344/5410] enabled
[INFO ] PCIe: Common Clock Configuration already enabled
[INFO ] PCIE CLK PM is not supported by endpoint
[INFO ] ASPM: Enabled L1
[EMERG] CPU Index 9 - APIC 32 Unexpected Exception:18 @ 10:76aeb93f - Halting
[EMERG] Code: 0 eflags: 00000046 cr2: 00000000
[EMERG] eax: 00000000 ebx: 00000009 ecx: 00000000 edx: 00000000
[EMERG] edi: 00000009 esi: 76b218c4 ebp: 00000000 esp: 76b29100
[EMERG] 0x76aeb8f8: c4 2c 5b 5e 5f 5d c3 56
[EMERG] 0x76aeb900: 53 83 ec 14 65 a1 00 00
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If2acdc16f37cdae0292f55d210b058f82179bfb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/prodrive/atlas/devicetree.cb')
-rw-r--r-- | src/mainboard/prodrive/atlas/devicetree.cb | 84 |
1 files changed, 48 insertions, 36 deletions
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index 86e86f5455..e9c818106f 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -71,62 +71,74 @@ chip soc/intel/alderlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" - # Enable PCH PCIE RP 5, 6, 7, 8, 9 using free running CLK (0x80) - # Clock source is shared hence marked as free running. - register "pch_pcie_rp[PCH_RP(5)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, - }" - register "pch_pcie_rp[PCH_RP(6)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, - }" - register "pch_pcie_rp[PCH_RP(7)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, - }" - register "pch_pcie_rp[PCH_RP(8)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, - }" - register "pch_pcie_rp[PCH_RP(9)]" = "{ - .flags = PCIE_RP_CLK_SRC_UNUSED, - }" + # Clock source 0 is shared between PCH RP 5, 6, 7, 8, 9 and CPU RP 1, 2, 3 + # Clock source 0 is therefore marked as FREE_RUNNING + # Set PCIE_RP_CLK_SRC_UNUSED on the root ports using clock source 0 so that + # we don't get a warning at boot about a missing clock definition. + register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" + + register "pch_pcie_rp[PCH_RP(5)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" + register "pch_pcie_rp[PCH_RP(6)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" + register "pch_pcie_rp[PCH_RP(7)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" + register "pch_pcie_rp[PCH_RP(8)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" + register "pch_pcie_rp[PCH_RP(9)].flags" = "PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_LTR | PCIE_RP_AER" # UFS or general purpose RP + + register "pch_pcie_rp[PCH_RP(5)].pcie_rp_aspm" = "ASPM_DISABLE" + register "pch_pcie_rp[PCH_RP(6)].pcie_rp_aspm" = "ASPM_DISABLE" + register "pch_pcie_rp[PCH_RP(7)].pcie_rp_aspm" = "ASPM_DISABLE" + register "pch_pcie_rp[PCH_RP(8)].pcie_rp_aspm" = "ASPM_DISABLE" + register "pch_pcie_rp[PCH_RP(9)].pcie_rp_aspm" = "ASPM_DISABLE" + + register "pch_pcie_rp[PCH_RP(5)].PcieRpL1Substates" = "L1_SS_DISABLED" + register "pch_pcie_rp[PCH_RP(6)].PcieRpL1Substates" = "L1_SS_DISABLED" + register "pch_pcie_rp[PCH_RP(7)].PcieRpL1Substates" = "L1_SS_DISABLED" + register "pch_pcie_rp[PCH_RP(8)].PcieRpL1Substates" = "L1_SS_DISABLED" + register "pch_pcie_rp[PCH_RP(9)].PcieRpL1Substates" = "L1_SS_DISABLED" + # Enable PCIe-to-i225 bridge using clk 1 + #TODO set clk_req, once it's connected on atlas. clk_req now defaults to 0, + # because using 0xFF (unused) would trigger a bug. register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, - .pcie_rp_aspm = ASPM_DISABLE, - }" - register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" - - # Enable CPU PCIE RP 1, 2, 3 using free running CLK (0x80) - # Clock source is shared hence marked as free running. - register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, - }" - register "cpu_pcie_rp[CPU_RP(2)]" = "{ - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, - }" - register "cpu_pcie_rp[CPU_RP(3)]" = "{ - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + .pcie_rp_aspm = ASPM_AUTO, }" device domain 0 on - device ref pcie5_0 on end + device ref pcie5_0 on + register "cpu_pcie_rp[CPU_RP(2)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" + register "cpu_pcie_rp[CPU_RP(2)].pcie_rp_aspm" = "ASPM_AUTO" + register "cpu_pcie_rp[CPU_RP(2)].PcieRpL1Substates" = "L1_SS_DISABLED" + end device ref igpu on end + # without DDT enabled, edk2 doesn't even finish (TODO) device ref dtt on end - device ref pcie4_0 on end - device ref pcie4_1 on end - device ref crashlog off end + device ref pcie4_0 on + register "cpu_pcie_rp[CPU_RP(1)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" + register "cpu_pcie_rp[CPU_RP(1)].pcie_rp_aspm" = "ASPM_DISABLE" + register "cpu_pcie_rp[CPU_RP(1)].PcieRpL1Substates" = "L1_SS_DISABLED" + end + device ref pcie4_1 on + register "cpu_pcie_rp[CPU_RP(3)].flags" = "PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED" + register "cpu_pcie_rp[CPU_RP(3)].pcie_rp_aspm" = "ASPM_DISABLE" + register "cpu_pcie_rp[CPU_RP(3)].PcieRpL1Substates" = "L1_SS_DISABLED" + end + # TODO try enabling crashlog + device ref crashlog on end device ref ish on end - device ref ufs on end + device ref ufs off end device ref tcss_xhci on end device ref xhci on end device ref heci1 on end device ref sata on end + # pcie_rp[1-4] is used for USB device ref pcie_rp5 on end device ref pcie_rp6 on end device ref pcie_rp7 on end device ref pcie_rp8 on end device ref pcie_rp9 on end device ref pcie_rp10 on end + # pcie_rp[11-12] is used for SATA device ref uart0 on end device ref uart1 on end device ref pch_espi on |