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authorFrans Hendriks <fhendriks@eltan.com>2019-07-15 08:48:55 +0200
committerMartin Roth <martinroth@google.com>2019-07-17 14:21:52 +0000
commited52e3dd9c33e5f714bde615e16c1b187cdd269f (patch)
treea19282a87dd1789b319ea0ac3612963148bb2983 /src/mainboard/portwell/m107/acpi/superio.asl
parent6feb4dadd85518c5e4603cb7da48ac4bec484c62 (diff)
mainboard/portwell/m107: Do initial mainboard commit
Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/portwell/m107/acpi/superio.asl')
-rw-r--r--src/mainboard/portwell/m107/acpi/superio.asl47
1 files changed, 47 insertions, 0 deletions
diff --git a/src/mainboard/portwell/m107/acpi/superio.asl b/src/mainboard/portwell/m107/acpi/superio.asl
new file mode 100644
index 0000000000..0258e28216
--- /dev/null
+++ b/src/mainboard/portwell/m107/acpi/superio.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "onboard.h"
+
+ Device (COM1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+ Name (_ADR, 0)
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ FixedIO (0x03F8, 0x08)
+ FixedIO (0x6E, 0x02)
+ IRQNoFlags () {4}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0, 0) {
+ FixedIO (0x03F8, 0x08)
+ FixedIO (0x6E, 0x02)
+ IRQNoFlags () {4}
+ }
+ EndDependentFn ()
+ })
+ }