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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/pcengines
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines')
-rw-r--r--src/mainboard/pcengines/apu2/BiosCallOuts.c8
-rw-r--r--src/mainboard/pcengines/apu2/mainboard.c8
-rw-r--r--src/mainboard/pcengines/apu2/romstage.c16
3 files changed, 16 insertions, 16 deletions
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 8a960cf6c7..3faa462cf1 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -72,7 +72,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
@@ -85,13 +85,13 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
oem_fan_control(FchParams);
/* XHCI configuration */
- FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;
/* EHCI configuration */
- FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)) {
+ if (CONFIG(BOARD_PCENGINES_APU2)) {
// Disable EHCI 0 (port 0 to 3)
FchParams->Usb.Ehci1Enable = FALSE;
} else {
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index 16bbf8a76b..472b864bd9 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -142,16 +142,16 @@ static void config_gpio_mux(void)
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
if (uart)
- uart->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_UART_C);
+ uart->enabled = CONFIG(APU2_PINMUX_UART_C);
if (gpio)
- gpio->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_GPIO0);
+ gpio->enabled = CONFIG(APU2_PINMUX_GPIO0);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
if (uart)
- uart->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_UART_D);
+ uart->enabled = CONFIG(APU2_PINMUX_UART_D);
if (gpio)
- gpio->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_GPIO1);
+ gpio->enabled = CONFIG(APU2_PINMUX_GPIO1);
}
/**********************************************
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 49281b905a..c449cc1ae9 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -79,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* COM2 on apu5 is reserved so only COM1 should be supported */
if ((CONFIG_UART_FOR_CONSOLE == 1) &&
- !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+ !CONFIG(BOARD_PCENGINES_APU5))
nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
else if (CONFIG_UART_FOR_CONSOLE == 0)
nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
@@ -143,13 +143,13 @@ static void early_lpc_init(void)
//
// Configure output disabled, value low, pull up/down disabled
//
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
+ if (CONFIG(BOARD_PCENGINES_APU5)) {
configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting);
}
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||
- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
+ if (CONFIG(BOARD_PCENGINES_APU2) ||
+ CONFIG(BOARD_PCENGINES_APU3) ||
+ CONFIG(BOARD_PCENGINES_APU4)) {
configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
}
@@ -161,8 +161,8 @@ static void early_lpc_init(void)
// Configure output enabled, value low, pull up/down disabled
//
setting = GPIO_OUTPUT_ENABLE;
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
+ if (CONFIG(BOARD_PCENGINES_APU3) ||
+ CONFIG(BOARD_PCENGINES_APU4)) {
configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
@@ -175,7 +175,7 @@ static void early_lpc_init(void)
//
setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
+ if (CONFIG(BOARD_PCENGINES_APU5)) {
configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}