diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-01-16 19:58:53 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-01-21 08:50:28 +0100 |
| commit | c27df8787801dac421b98c4dbb447e519065ae95 (patch) | |
| tree | bed7950203810f7140a7a817b851183f8bc5c643 /src/mainboard/pcengines | |
| parent | 0a06205ec65ea626ab94fa67680476266890044b (diff) | |
pcengines/apu2: Refactor reading memory strap
Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18152
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/pcengines')
| -rw-r--r-- | src/mainboard/pcengines/apu2/BiosCallOuts.c | 13 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu2/gpio_ftns.c | 14 | ||||
| -rw-r--r-- | src/mainboard/pcengines/apu2/gpio_ftns.h | 1 |
3 files changed, 18 insertions, 10 deletions
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index bba814412a..fe64d64449 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -22,6 +22,7 @@ #include "heapManager.h" #include "FchPlatform.h" #include "cbfs.h" +#include "gpio_ftns.h" #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) #include "imc.h" #endif @@ -125,13 +126,12 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) return AGESA_SUCCESS; } - static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status = AGESA_UNSUPPORTED; #ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; - int index = 0; + u8 index = get_spd_offset(); if (info->MemChannelId > 0) return AGESA_UNSUPPORTED; @@ -140,14 +140,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf if (info->DimmId != 0) return AGESA_UNSUPPORTED; - /* One SPD file contains all 4 options, determine which index to read here, then call into the standard routines*/ - - u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE); - if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0; - if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1; - - printk(BIOS_INFO, "Reading SPD index %d\n", index); - + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index fd1fb3c9e2..12b8f9464b 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/io.h> #include <southbridge/amd/cimx/cimx_util.h> +#include "FchPlatform.h" #include "gpio_ftns.h" void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) @@ -32,3 +33,16 @@ void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, bdata |= setting; /* set direction and data value */ *memptr = bdata; } + +int get_spd_offset(void) +{ + u8 index = 0; + /* One SPD file contains all 4 options, determine which index to + * read here, then call into the standard routines. + */ + u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE); + if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0; + if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1; + + return index; +} diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 4f0cbaaa62..181349609d 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -17,6 +17,7 @@ #define GPIO_FTNS_H void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); +int get_spd_offset(void); #define IOMUX_OFFSET 0xD00 #define GPIO_OFFSET 0x1500 |