sb/amd/cimx: replace cimx_util with common ACPIMMIO AMD block

Drop the redundant cimx_util, remove the includes when appropriate and
replace the implementation with amdblocks/acpimmio where needed.

TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 10 insertions, 19 deletions

diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c
index 7a988e7ec6..bedd15a514 100644
--- a/src/mainboard/pcengines/apu1/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu1/gpio_ftns.c
@@ -14,25 +14,18 @@
  */
 
 #include <stdint.h>
+#include <amdblocks/acpimmio.h>
 #include <arch/io.h>
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/cimx/cimx_util.h>
 #include "gpio_ftns.h"
 
 uintptr_t find_gpio_base(void)
 {
-	u8 pm_index, pm_data;
-	uintptr_t base_addr = 0;
-
-	/* Find the ACPImmioAddr base address */
-	for (pm_index = 0x27; pm_index > 0x23; pm_index--) {
-		outb(pm_index, PM_INDEX);
-		pm_data = inb(PM_DATA);
-		base_addr <<= 8;
-		base_addr |= (u32)pm_data;
-	}
+	uintptr_t base_addr;
+	/* Get the ACPIMMIO base address */
+	base_addr = pm_read32(0x24);
 	base_addr &= 0xFFFFF000;
-	return (base_addr);
+	return base_addr;
 }
 
 void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting)
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 088c839239..1c302912a9 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -21,7 +21,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/common/amd_pci_util.h>
-#include <southbridge/amd/cimx/cimx_util.h>
 #include <smbios.h>
 #include <string.h>
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index ab48943c55..89bf3049d6 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -15,8 +15,8 @@
  * GNU General Public License for more details.
  */
 
+#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/cimx/cimx_util.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"
@@ -33,16 +33,16 @@ static void early_lpc_init(void)
 	 * controlled in PM_REG 5Bh register. "Always Power On" works by writing a
 	 * value of 05h.
 	 */
-	u8 bdata = pm_ioread(SB_PMIOA_REG5B);
+	u8 bdata = pm_read8(SB_PMIOA_REG5B);
 	bdata &= 0xf8; //clear bits 0-2
 	bdata |= 0x05; //set bits 0,2
-	pm_iowrite(SB_PMIOA_REG5B, bdata);
+	pm_write8(SB_PMIOA_REG5B, bdata);
 
 	/* Multi-function pins switch to GPIO0-35, these pins are shared with PCI pins */
-	bdata = pm_ioread(SB_PMIOA_REGEA);
+	bdata = pm_read8(SB_PMIOA_REGEA);
 	bdata &= 0xfe; //clear bit 0
 	bdata |= 0x01; //set bit 0
-	pm_iowrite(SB_PMIOA_REGEA, bdata);
+	pm_write8(SB_PMIOA_REGEA, bdata);
 
 	//configure required GPIOs
 	mmio_base = find_gpio_base();
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
index a1e2e51952..249ecc3494 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <device/mmio.h>
-#include <southbridge/amd/cimx/cimx_util.h>
 #include <FchPlatform.h>
 #include "gpio_ftns.h"