AGESA,binaryPI boards: Drop invalid MP table files

If we spot any error in the file, treat it as untested and
broken copy-paste.

Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 0 insertions, 233 deletions

diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 04019d22d4..2c6e657db6 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOUTHBRIDGE_AMD_CIMX_SB800
 	select SUPERIO_NUVOTON_NCT5104D
 	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_OPTION_TABLE
diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c
deleted file mode 100644
index 52aca2ef66..0000000000
--- a/src/mainboard/pcengines/apu1/mptable.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/smp/mpspec.h>
-#include <stdint.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <arch/ioapic.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/*
-	 * By the time this function gets called, the IOAPIC registers
-	 * have been written so they can be read to get the correct
-	 * APIC ID and Version
-	 */
-	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
-	/* Initialize the MP_Table */
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	/*
-	 * Type 0: Processor Entries:
-	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
-	 * CPU Signature (Stepping, Model, Family),
-	 * Feature Flags
-	 */
-	smp_write_processors(mc);
-
-	/*
-	 * Type 1: Bus Entries:
-	 * Bus ID, Bus Type
-	 */
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * Type 2: I/O APICs:
-	 * APIC ID, Version, APIC Flags:EN, Address
-	 */
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
-	/*
-	 * Type 3: I/O Interrupt Table Entries:
-	 * Int Type, Int Polarity, Int Level, Source Bus ID,
-	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
-	 */
-	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, fn, pin) \
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
-
-	/* APU Internal Graphic Device */
-	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
-	/* SMBUS / ACPI */
-	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
-	/* Southbridge HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
-	/* LPC */
-	PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
-	PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
-	PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
-	PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
-
-	 /* IDE */
-	PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
-	/* on board NIC & Slot PCIE */
-	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
-	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
-	PCI_INT(0x3, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
-	PCI_INT(0x4, 0x0, 0x0, intr_data_ptr[PIRQ_E]);	/* Use INTE */
-
-	/* PCIe PortA */
-	PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]);	/* INTA -> INTE */
-	/* PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]);	/* INTB -> INTF */
-	/* PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]);	/* INTC -> INTG */
-	/* PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]);	/* INTD -> INTH */
-
-	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-		smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);	/* ADDR, Enable Virtual Wire */
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index fde73405c4..875c01c837 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select DEFAULT_POST_ON_LPC
 	select SUPERIO_NUVOTON_NCT5104D
 	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_8192
 	select HAVE_SPD_IN_CBFS
diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
deleted file mode 100644
index a24863f5e3..0000000000
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <northbridge/amd/nb_common.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/* Initialize the MP_Table */
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	/*
-	 * Type 0: Processor Entries:
-	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
-	 * CPU Signature (Stepping, Model, Family),
-	 * Feature Flags
-	 */
-	smp_write_processors(mc);
-
-	/*
-	 * Type 1: Bus Entries:
-	 * Bus ID, Bus Type
-	 */
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * Type 2: I/O APICs:
-	 * APIC ID, Version, APIC Flags:EN, Address
-	 */
-	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
-	ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24);
-	ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF);
-
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR);
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin)				\
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	/*
-	 * Type 3: I/O Interrupt Table Entries:
-	 * Int Type, Int Polarity, Int Level, Source Bus ID,
-	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
-	 */
-
-	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin)				\
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-	/* SMBUS / ACPI */
-	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
-	/* SD card */
-	PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_SD]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
-	/* on board NIC & Slot PCIE */
-	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
-	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-	/* GPP0 */
-	PCI_INT(0x0, 0x2, 0x0, 0x10);	// Network 3
-	/* GPP1 */
-	PCI_INT(0x0, 0x2, 0x1, 0x11);	// Network 2
-	/* GPP2 */
-	PCI_INT(0x0, 0x2, 0x2, 0x12);	// Network 1
-	/* GPP3 */
-	PCI_INT(0x0, 0x2, 0x3, 0x13);	// mPCI
-	/* GPP4 */
-	PCI_INT(0x0, 0x2, 0x4, 0x14);	// mPCI
-
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);	/* ADDR, Enable Virtual Wire */
-	return (unsigned long)smp_write_config_table(v);
-}