diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/pcengines/apu2/romstage.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/romstage.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 49281b905a..c449cc1ae9 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -79,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* COM2 on apu5 is reserved so only COM1 should be supported */ if ((CONFIG_UART_FOR_CONSOLE == 1) && - !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) + !CONFIG(BOARD_PCENGINES_APU5)) nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); else if (CONFIG_UART_FOR_CONSOLE == 0) nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); @@ -143,13 +143,13 @@ static void early_lpc_init(void) // // Configure output disabled, value low, pull up/down disabled // - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { + if (CONFIG(BOARD_PCENGINES_APU5)) { configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting); } - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { + if (CONFIG(BOARD_PCENGINES_APU2) || + CONFIG(BOARD_PCENGINES_APU3) || + CONFIG(BOARD_PCENGINES_APU4)) { configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); } @@ -161,8 +161,8 @@ static void early_lpc_init(void) // Configure output enabled, value low, pull up/down disabled // setting = GPIO_OUTPUT_ENABLE; - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) || - IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) { + if (CONFIG(BOARD_PCENGINES_APU3) || + CONFIG(BOARD_PCENGINES_APU4)) { configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); } @@ -175,7 +175,7 @@ static void early_lpc_init(void) // setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE; - if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) { + if (CONFIG(BOARD_PCENGINES_APU5)) { configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); } |