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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-04-04 08:49:21 +0000 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-04-07 12:07:15 +0000 |
| commit | 869ac71483616cd363170cdf2cf5d4ce1965a2a1 (patch) | |
| tree | e386332a5385466ae8b067fec7a5291be8503ddd /src/mainboard/pcengines/apu2/romstage.c | |
| parent | 7daf3cd32e259889c0cb419b4440422649d82266 (diff) | |
Revert "mb/pcengines/apu2: add reset logic for PCIe slots"
This reverts commit c04871a398ca945b42fde0867572094c38f6f92c.
Reason for revert: Many apu2 users reported issues with PCIe modules
detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught
by 3mdeb validation stands and hardware configuration.
Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/pcengines/apu2/romstage.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 6ba5712bd6..e40d95df16 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -27,15 +27,6 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Release GPIO32/33 for other uses. */ pm_write8(0xea, 1); - - /* - * Assert resets on the PCIe slots, since AGESA calls deassert callout - * only. Only apu2 uses GPIOs to reset PCIe slots. - */ - if (CONFIG(BOARD_PCENGINES_APU2)) { - gpio1_write8(0xa, gpio1_read8(0xa) & ~(1 << 6)); - gpio1_write8(0xe, gpio1_read8(0xe) & ~(1 << 6)); - } } static void early_lpc_init(void) |