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authorMAULIK V VAGHELA <maulik.v.vaghela@intel.com>2021-11-25 14:41:19 +0530
committerFelix Held <felix-coreboot@felixheld.de>2021-12-13 13:57:39 +0000
commita70288d9fc60416d828a724fd1f2e871bd9cc129 (patch)
tree65200a307e8867f6edfe51075768d2e558453caa /src/mainboard/pcengines/apu2/mainboard.c
parent32f883e53275320f5b023bc9027da0db127874b8 (diff)
drivers/intel/usb4/retimer: Add function to correct EC port mapping
Currently coreboot interprets TCSS port number as per physical port number while EC abstracts port number and provides indices as port number. For example, if TCSS port 1 and 3 are enabled on the board, coreboot will interpret port numbers as 0 and 2, but since only 2 ports are enabled in the system EC will assign port numbers as 0 and 1. This creates a port number mismatch while communicating between EC and coreboot. This patch addresses issue where SoC can implement function to map correct EC port as per port enabled in mainboard. BUG=b:207057940 BRANCH=None TEST=Check if code compiles successfully. Functionality will work once function is implemented in SoC code. Change-Id: Ia7a5e63838e6529196bd211516e4d665b084f79e Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/pcengines/apu2/mainboard.c')
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