diff options
| author | Kamil Wcislo <kamil.wcislo@3mdeb.com> | 2017-10-12 11:55:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-20 02:19:23 +0000 |
| commit | 70b92456eb2f507b6d6ce24212219e7dfbb59747 (patch) | |
| tree | f4eb46df82cf87dffb01e1202d118f491d8eb92c /src/mainboard/pcengines/apu2/gpio_ftns.h | |
| parent | 6a35fab2723f3b1ca288cd9224d263570cfbe184 (diff) | |
mainboard/pcengines/apu2: add apu3 and apu5 variants
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).
This patch adds support for those other variants by not introducing
additional code redundancy.
Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/gpio_ftns.h')
| -rw-r--r-- | src/mainboard/pcengines/apu2/gpio_ftns.h | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 181349609d..e08ee7bcac 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -23,33 +23,36 @@ int get_spd_offset(void); #define GPIO_OFFSET 0x1500 // -// Based on PC Engines APU2C schematics +// Based on PC Engines APU2C and APU3A schematics // http://www.pcengines.ch/schema/apu2c.pdf +// http://www.pcengines.ch/schema/apu3a.pdf // -#define IOMUX_GPIO_32 0x59 // MODESW +#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) +#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) #define IOMUX_GPIO_49 0x40 // STRAP0 #define IOMUX_GPIO_50 0x41 // STRAP1 -#define IOMUX_GPIO_51 0x42 // PE3 Reset -#define IOMUX_GPIO_55 0x43 // PE4 Reset +#define IOMUX_GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5) +#define IOMUX_GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5) #define IOMUX_GPIO_57 0x44 // LED1# #define IOMUX_GPIO_58 0x45 // LED2# #define IOMUX_GPIO_59 0x46 // LED3# -#define IOMUX_GPIO_64 0x47 // PE3_WDIS +#define IOMUX_GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5) #define IOMUX_GPIO_66 0x5B // SPKR -#define IOMUX_GPIO_68 0x48 // PE4_WDIS +#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) #define IOMUX_GPIO_71 0x4D // PROCHOT -#define GPIO_32 0x164 // MODESW +#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5) +#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5) #define GPIO_49 0x100 // STRAP0 #define GPIO_50 0x104 // STRAP1 -#define GPIO_51 0x108 // PE3 Reset -#define GPIO_55 0x10C // PE4 Reset +#define GPIO_51 0x108 // PE3 Reset (SIM1 Reset on APU5) +#define GPIO_55 0x10C // PE4 Reset (SIM2 Reset on APU5) #define GPIO_57 0x110 // LED1# #define GPIO_58 0x114 // LED2# #define GPIO_59 0x118 // LED3# -#define GPIO_64 0x11C // PE3_WDIS +#define GPIO_64 0x11C // PE3_WDIS (SIM3 Reset on APU5) #define GPIO_66 0x16C // SPKR -#define GPIO_68 0x120 // PE4_WDIS +#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5) #define GPIO_71 0x134 // PROCHOT #define GPIO_OUTPUT_ENABLE 23 |