pcengines/apu2: add board support

Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.

Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.

memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.

SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872

SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.

Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder

Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 59 insertions, 0 deletions

diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
new file mode 100644
index 0000000000..4f0cbaaa62
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef GPIO_FTNS_H
+#define GPIO_FTNS_H
+
+void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+
+#define IOMUX_OFFSET    0xD00
+#define GPIO_OFFSET     0x1500
+
+//
+// Based on PC Engines APU2C schematics
+// http://www.pcengines.ch/schema/apu2c.pdf
+//
+#define IOMUX_GPIO_32   0x59    // MODESW
+#define IOMUX_GPIO_49   0x40    // STRAP0
+#define IOMUX_GPIO_50   0x41    // STRAP1
+#define IOMUX_GPIO_51   0x42    // PE3 Reset
+#define IOMUX_GPIO_55   0x43    // PE4 Reset
+#define IOMUX_GPIO_57   0x44    // LED1#
+#define IOMUX_GPIO_58   0x45    // LED2#
+#define IOMUX_GPIO_59   0x46    // LED3#
+#define IOMUX_GPIO_64   0x47    // PE3_WDIS
+#define IOMUX_GPIO_66   0x5B    // SPKR
+#define IOMUX_GPIO_68   0x48    // PE4_WDIS
+#define IOMUX_GPIO_71   0x4D    // PROCHOT
+
+#define GPIO_32   0x164    // MODESW
+#define GPIO_49   0x100    // STRAP0
+#define GPIO_50   0x104    // STRAP1
+#define GPIO_51   0x108    // PE3 Reset
+#define GPIO_55   0x10C    // PE4 Reset
+#define GPIO_57   0x110    // LED1#
+#define GPIO_58   0x114    // LED2#
+#define GPIO_59   0x118    // LED3#
+#define GPIO_64   0x11C    // PE3_WDIS
+#define GPIO_66   0x16C    // SPKR
+#define GPIO_68   0x120    // PE4_WDIS
+#define GPIO_71   0x134    // PROCHOT
+
+#define GPIO_OUTPUT_ENABLE      23
+#define GPIO_OUTPUT_VALUE       22
+#define GPIO_PULL_DOWN_ENABLE   21
+#define GPIO_PULL_UP_ENABLE     20
+
+#endif /* GPIO_FTNS_H */