diff options
| author | Kamil Wcislo <kamil.wcislo@3mdeb.com> | 2017-10-12 11:55:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-20 02:19:23 +0000 |
| commit | 70b92456eb2f507b6d6ce24212219e7dfbb59747 (patch) | |
| tree | f4eb46df82cf87dffb01e1202d118f491d8eb92c /src/mainboard/pcengines/apu2/devicetree.cb | |
| parent | 6a35fab2723f3b1ca288cd9224d263570cfbe184 (diff) | |
mainboard/pcengines/apu2: add apu3 and apu5 variants
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).
This patch adds support for those other variants by not introducing
additional code redundancy.
Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/devicetree.cb')
| -rw-r--r-- | src/mainboard/pcengines/apu2/devicetree.cb | 94 |
1 files changed, 0 insertions, 94 deletions
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb deleted file mode 100644 index 4f3206408e..0000000000 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ /dev/null @@ -1,94 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2013 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end - end - - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 off end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # mPCIe slot 2 (on GFX lane) - device pci 2.2 on end # LAN3 - device pci 2.3 on end # LAN2 - device pci 2.4 on end # LAN1 - device pci 2.5 on end # mPCIe slot 1 - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 - - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 muxed with EHCI 2 - device pci 11.0 on end # SATA - device pci 12.0 off end # USB EHCI0 usb[0:3] not connected - device pci 13.0 on end # USB EHCI1 usb[4:7] - device pci 14.0 on end # SM - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 on - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 on - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 on end - device pnp 2e.107 on end - device pnp 2e.607 off end - device pnp 2e.e off end - end # SIO NCT5104D - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end # LPC TPM - end # LPC 0x439d - - device pci 14.7 on end # SD - device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - end #domain -end #northbridge/amd/pi/00730F01/root_complex |