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author | Piotr Król <piotr.krol@3mdeb.com> | 2016-05-27 12:04:13 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-19 10:11:13 +0100 |
commit | dcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5 (patch) | |
tree | 8ca75267ff1c0fa136680bbe7a87dd8b58e697ee /src/mainboard/pcengines/apu2/acpi/mainboard.asl | |
parent | cff3b095c2fdb7af7b6fb0a1e09c2a66c1ad1c67 (diff) |
pcengines/apu2: add board support
Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.
Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.
memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.
SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872
SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.
Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/acpi/mainboard.asl')
-rw-r--r-- | src/mainboard/pcengines/apu2/acpi/mainboard.asl | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/acpi/mainboard.asl b/src/mainboard/pcengines/apu2/acpi/mainboard.asl new file mode 100644 index 0000000000..0141481d06 --- /dev/null +++ b/src/mainboard/pcengines/apu2/acpi/mainboard.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} |