diff options
| author | Kamil Wcislo <kamil.wcislo@3mdeb.com> | 2017-10-12 11:55:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-20 02:19:23 +0000 |
| commit | 70b92456eb2f507b6d6ce24212219e7dfbb59747 (patch) | |
| tree | f4eb46df82cf87dffb01e1202d118f491d8eb92c /src/mainboard/pcengines/apu2/BiosCallOuts.c | |
| parent | 6a35fab2723f3b1ca288cd9224d263570cfbe184 (diff) | |
mainboard/pcengines/apu2: add apu3 and apu5 variants
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).
This patch adds support for those other variants by not introducing
additional code redundancy.
Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu2/BiosCallOuts.c')
| -rw-r--r-- | src/mainboard/pcengines/apu2/BiosCallOuts.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 071de97e99..8e2636bdfc 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -90,8 +90,18 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) /* EHCI configuration */ FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams->Usb.Ehci1Enable = FALSE; // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci2Enable = TRUE; // Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + + if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } + + // Enable EHCI 1 ( port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; /* sata configuration */ FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP |