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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-03 14:06:02 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-13 08:58:12 +0000
commit3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09 (patch)
tree98196a78b5aed35d8c238cfb6b86668506e526e5 /src/mainboard/pcengines/apu1
parent24f0455016720e4222057ecda3415c05c7cb095c (diff)
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1')
-rw-r--r--src/mainboard/pcengines/apu1/romstage.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 89bf3049d6..da0e0d3d5e 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -21,6 +21,7 @@
#include <superio/nuvoton/nct5104d/nct5104d.h>
#include "gpio_ftns.h"
#include <SB800.h>
+#include <sb_cimx.h>
#define SIO_PORT 0x2e
#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
@@ -60,6 +61,7 @@ static void early_lpc_init(void)
void board_BeforeAgesa(struct sysinfo *cb)
{
+ sb_Poweron_Init();
early_lpc_init();
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}