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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-17 18:08:40 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-23 21:36:21 +0100 |
| commit | b5a8a13bde537893d1bf150b2d90156e4b855374 (patch) | |
| tree | b9ac3ba97d1dc10aa04bf53c26711bd073e3cb75 /src/mainboard/pcengines/apu1/platform_cfg.h | |
| parent | 07354235df303c0c1ea3845f5325993a089b4150 (diff) | |
pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.
Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.
Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/platform_cfg.h')
| -rw-r--r-- | src/mainboard/pcengines/apu1/platform_cfg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 08051ec5b7..df2b0ecf30 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -185,7 +185,7 @@ * GPP_CFGMODE_X2110 * GPP_CFGMODE_X1111 */ -#define GPP_CFGMODE GPP_CFGMODE_X4000 +#define GPP_CFGMODE GPP_CFGMODE_X1111 /** * @def NB_SB_GEN2 @@ -206,7 +206,7 @@ * TRUE - ports visible always, even port empty * FALSE - ports invisible if port empty */ -#define SB_GPP_UNHIDE_PORTS TRUE +#define SB_GPP_UNHIDE_PORTS FALSE /** * @def GEC_CONFIG |