diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-11 17:22:23 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-23 21:34:55 +0100 |
| commit | 780935687d74f89a25a9c58952314be6af61c348 (patch) | |
| tree | 193897842085f03675cb6b97e1f9ca523abb7a83 /src/mainboard/pcengines/apu1/mainboard.c | |
| parent | 8c190f3518d504d904692e93e7881c379b89f542 (diff) | |
pcengines/apu1: Implement board GPIOs
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/mainboard.c')
| -rw-r--r-- | src/mainboard/pcengines/apu1/mainboard.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index cf0d82300e..01a0bd2ef2 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -33,6 +33,7 @@ #include "SBPLATFORM.h" #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> +#include "gpio_ftns.h" void set_pcie_reset(void); void set_pcie_dereset(void); @@ -161,6 +162,24 @@ static void mainboard_enable(device_t dev) pirq_setup(); } +static void mainboard_final(void *chip_info) +{ + u32 mmio_base; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n"); + + /* + * LED1/D7/GPIO_189 should be 0 + * LED2/D6/GPIO_190 should be 1 + * LED3/D5/GPIO_191 should be 1 + */ + mmio_base = find_gpio_base(); + configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW); + configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); + configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .final = mainboard_final, }; |