diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 17:42:04 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-12 19:28:33 +0000 |
| commit | af258cc1791b5c46fcb13d41128cc99043a435be (patch) | |
| tree | 3c143244682d60fed4172086832ae9e4ad66fd76 /src/mainboard/pcengines/apu1/mainboard.c | |
| parent | cbbfb702f693c1bbaf83a9d3d8a3c0caabda1814 (diff) | |
mb/*/*: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/mainboard.c')
| -rw-r--r-- | src/mainboard/pcengines/apu1/mainboard.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 854fb8ad4d..0528468e5d 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/acpimmio.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -181,17 +182,17 @@ static void mainboard_enable(struct device *dev) config_gpio_mux(); config_addon_uart(); - /* Power off unused clock pins of GPP PCIe devices */ - u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); - /* GPP CLK0-2 are connected to the 3 ethernet chips - * GPP CLK3-4 are connected to the miniPCIe slots */ - write8(misc_mem_clk_cntrl + 0, 0x21); - write8(misc_mem_clk_cntrl + 1, 0x43); + /* Power off unused clock pins of GPP PCIe devices + * GPP CLK0-2 are connected to the 3 ethernet chips + * GPP CLK3-4 are connected to the miniPCIe slots + */ + misc_write8(0, 0x21); + misc_write8(1, 0x43); /* GPP CLK5 is only connected to test pads -> disable */ - write8(misc_mem_clk_cntrl + 2, 0x05); + misc_write8(2, 0x05); /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ - write8(misc_mem_clk_cntrl + 3, 0x00); - write8(misc_mem_clk_cntrl + 4, 0x00); + misc_write8(3, 0); + misc_write8(4, 0); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); |