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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-11 22:53:19 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-05-19 14:46:58 +0200 |
commit | 017c2150d4a528c58a454705db74210477623a5f (patch) | |
tree | d26524851cb6d57a48dc951e1a160904edc995d6 /src/mainboard/pcengines/apu1/devicetree.cb | |
parent | 58d5e21851ced6b475a87e3a4114b2c7e1125921 (diff) |
pcengines/apu1: Add switch between UART and GPIO modes
These are alternative customer options connected to J19 header.
We need to avoid modifying devicetree.cb, so we fix devicetree
for the super-io device-enables at runtime instead.
Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/devicetree.cb')
-rw-r--r-- | src/mainboard/pcengines/apu1/devicetree.cb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index b98f34d4d1..1f07a9b016 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -59,16 +59,19 @@ chip northbridge/amd/agesa/family14/root_complex irq 0x70 = 3 end device pnp 2e.10 off + # UART C is conditionally turned on io 0x60 = 0x3e8 irq 0x70 = 4 end device pnp 2e.11 off + # UART D is conditionally turned on io 0x60 = 0x2e8 irq 0x70 = 3 end device pnp 2e.8 off end device pnp 2e.f off end - device pnp 2e.7 off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end device pnp 2e.e off end |