diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-14 16:20:22 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-23 21:34:21 +0100 |
| commit | 8c190f3518d504d904692e93e7881c379b89f542 (patch) | |
| tree | 007e007823bc87be9416573c389cf05259a5e212 /src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h | |
| parent | f09e6d47b8174017d8964780b916dec9dd0b2009 (diff) | |
pcengines/apu1: New board PC Engines APU1
While we cannot recreate exact copies of PC Engines APU1 firmware images,
I shall upstream the vital changes for coreboot from the following tarballs
SAGE has published to meet GPL:
SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz
md5sum: ce5f54723e4fe3b63a1a3e35586728d4
pcengines.apu_139_osp.tar.gz
md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef
The patch here adds Kconfig, Makefile.inc and devicetree.cb files to
match 2014/04/05 release tarball config.h and static.c files.
Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h')
| -rw-r--r-- | src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h index 4a01875920..89a41a1e18 100644 --- a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h +++ b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,7 +51,7 @@ #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) |