Random minor cosmetical or coding style fixes (trivial).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 42 insertions, 35 deletions

diff --git a/src/mainboard/pcengines/alix1c/irq_tables.c b/src/mainboard/pcengines/alix1c/irq_tables.c
index 55d2823085..1db35cba45 100644
--- a/src/mainboard/pcengines/alix1c/irq_tables.c
+++ b/src/mainboard/pcengines/alix1c/irq_tables.c
@@ -20,7 +20,6 @@
 #include <arch/pirq_routing.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <arch/pirq_routing.h>
 #include "../../../southbridge/amd/cs5536/cs5536.h"
 
 /* Platform IRQs */
@@ -41,7 +40,11 @@
 #define L_PIRQC 3		/* Means Slot INTx# Connects To Chipset INTC# */
 #define L_PIRQD 4		/* Means Slot INTx# Connects To Chipset INTD# */
 
-/* ALIX 1c interrupt wiring. Devices are:
+/*
+ * ALIX1.C interrupt wiring.
+ *
+ * Devices are:
+ *
  * 00:01.0 Host bridge: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge (rev 31)
  * 00:01.2 Entertainment encryption device: Advanced Micro Devices [AMD] Geode LX AES Security Block
  * 00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6105M [Rhine-III] (rev 96)
@@ -51,8 +54,11 @@
  * 00:0f.3 Multimedia audio controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] Audio (rev 01)
  * 00:0f.4 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC (rev 02)
  * 00:0f.5 USB Controller: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
+ *
  * The only devices that interrupt are:
- * What         device  IRQ     PIN     PIN WIRED TO
+ *
+ * What         Device  IRQ     PIN     PIN WIRED TO
+ * -------------------------------------------------
  * AES          00:01.2 0a      01      A       A
  * 3VPCI        00:0c.0 0a      01      A       A
  * eth0 	00:0d.0 0b      01      A       B
@@ -61,39 +67,40 @@
  * usb          00:0f.4 0b      04      D       D
  * usb          00:0f.5 0b      04      D       D
  *
- * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B
-*/
+ * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
+ */
+
 const struct irq_routing_table intel_irq_routing_table = {
-PIRQ_SIGNATURE,		/* u32 signature */
-PIRQ_VERSION,		/* u16 version   */
-32 + 16 * IRQ_SLOT_COUNT,
-0x00,			/* Where the interrupt router lies (bus) */
-(0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
-0x00,			/* IRQs devoted exclusively to PCI usage */
-0x100B,			/* Vendor */
-0x002B,			/* Device */
-0,			/* Crap (miniport) */
-{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
-0x00,			/* u8 checksum , this has to set to 
-			 * some value that would give 0 
-			 * after the sum of all bytes 
-			 * for this structure 
-			 * (including checksum) 
-			 */
-{
-	/* If you change the number of entries, 
-	 * change the IRQ_SLOT_COUNT above! 
-	 */
-	/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* cpu */
-		/* PCI SLOT */
-		{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},	/* slot1 */
-		/* ONBOARD ETHER */
-		{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* ethernet */
-		/* MINI PCI */
-		{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},	/* mini slot2 */
-		/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D */
-		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
+	PIRQ_SIGNATURE,
+	PIRQ_VERSION,
+	32 + 16 * IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
+	0x00,			/* Where the interrupt router lies (bus) */
+	(0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
+	0x00,			/* IRQs devoted exclusively to PCI usage */
+	0x100B,			/* Vendor */
+	0x002B,			/* Device */
+	0,			/* Crap (miniport) */
+	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
+	0x00,			/* Checksum */
+	{
+		/* If you change the number of entries, change IRQ_SLOT_COUNT above! */
+
+		/* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
+
+		/* CPU */
+		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* PCI (slot 1) */
+		{0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x4, 0x0},
+
+		/* On-board ethernet */
+		{0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
+
+		/* Mini PCI (slot 2) */
+		{0x00, (0x0E << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x1, 0x0},
+
+		/* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
+		{0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
 	}
 };