diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-02 00:21:01 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:13:21 +0000 |
| commit | d0310faa3bc4d3b62d17d632fbaee98c146eebe0 (patch) | |
| tree | 8d3a55eb4135484ae7729f8092876ba36c165a2e /src/mainboard/packardbell/ms2290 | |
| parent | f266dc61743cfce56ea026e66bc88cad8e5de2bb (diff) | |
sb/intel/ibexpeak: Implement PCH function disable in chip_ops
This does the following:
- implement a PCH disable function that will be called by the PCI
drivers as part of their chip_ops
- removes the iobp_x calls as those don't exist on ibexpeak
- complete the devicetree with to be disabled PCI devices for the
chip_ops to be called
- Clean up some code copied from bd82x6x
Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/packardbell/ms2290')
| -rw-r--r-- | src/mainboard/packardbell/ms2290/devicetree.cb | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index c98f9a36bc..bf1c171222 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -66,6 +66,13 @@ chip northbridge/intel/nehalem register "alt_gp_smi_en" = "0x0000" register "gen1_dec" = "0x040069" + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R, only management boot + device pci 16.3 off end # Management Engine KT + + device pci 19.0 off end # Ethernet + device pci 1a.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end @@ -75,11 +82,18 @@ chip northbridge/intel/nehalem end device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 off end + device pci 1c.3 off end + device pci 1c.4 off end + device pci 1c.5 off end + device pci 1c.6 off end + device pci 1c.7 off end device pci 1d.0 on # USB2 EHCI subsystemid 0x1025 0x0379 end + device pci 1e.0 on end # PCI 2 PCI bridge device pci 1f.0 on # PCI-LPC bridge subsystemid 0x1025 0x0379 end @@ -89,6 +103,9 @@ chip northbridge/intel/nehalem device pci 1f.3 on # SMBUS subsystemid 0x1025 0x0379 end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end end end end |