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authorPhilipp Deppenwiese <zaolin@das-labor.org>2018-07-28 19:13:04 +0200
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-07-28 18:18:18 +0000
commitdf1a0652152f603d8147ab91017ab454db5512a7 (patch)
tree111ff4c969cc052120f16de933edf350f8c5ee42 /src/mainboard/opencellular/rotundu/variants
parent660dd0007953916d82ff66c238dc30e610f45c08 (diff)
mainboard/opencellular/rotundu: Enable TPM 1.2 support
* Enable support for all variants. Change-Id: Ibdd43d8cff23d3fa1154e2b72aa6095682783fe5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/opencellular/rotundu/variants')
-rw-r--r--src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb6
-rw-r--r--src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb6
2 files changed, 10 insertions, 2 deletions
diff --git a/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb
index a31a001657..7eeac7ad84 100644
--- a/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb
+++ b/src/mainboard/opencellular/rotundu/variants/rotundu/devicetree.cb
@@ -75,7 +75,11 @@ chip soc/intel/fsp_baytrail
device pci 1e.3 on end # 8086 0F0A - HSUART 1
device pci 1e.4 off end # 8086 0F0C - HSUART 2
device pci 1e.5 off end # 8086 0F0E - SPI
- device pci 1f.0 on end # 8086 0F1C - LPC bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # 8086 0F1C - LPC bridge
device pci 1f.3 on end # 8086 0F12 - SMBus 0
end
end
diff --git a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
index df089229f4..c0bd2f0fe2 100644
--- a/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
+++ b/src/mainboard/opencellular/rotundu/variants/supabrckv1/devicetree.cb
@@ -75,7 +75,11 @@ chip soc/intel/fsp_baytrail
device pci 1e.3 on end # 8086 0F0A - HSUART 1
device pci 1e.4 off end # 8086 0F0C - HSUART 2
device pci 1e.5 off end # 8086 0F0E - SPI
- device pci 1f.0 on end # 8086 0F1C - LPC bridge
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end # 8086 0F1C - LPC bridge
device pci 1f.3 on end # 8086 0F12 - SMBus 0
end
end